IndiumV3, Chine, Analysis, bibRecord, 000803

Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells

Identifieur interne : 000803 ( Chine/Analysis ); précédent : 000802; suivant : 000804

Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells

Auteurs : RBID : Pascal:11-0367449

Descripteurs français

Pascal (Inist)
- Cellule solaire, Technologie MOS complémentaire, Circuit intégré monolithique, Evaluation performance, Adhérence, Topographie surface, Contrainte thermique, Contrainte mécanique, Surface arrière, Récupération énergie, Système intelligent, Cuivre, Séléniure d'indium, Séléniure de gallium, Verre, Séléniure de cuivre, GaSe.
Wicri :
- concept : Cuivre, Verre.

English descriptors

KwdEn :
- Adhesion, Back surface, Complementary MOS technology, Copper, Copper selenides, Energy recovery, Gallium selenides, Glass, Indium selenides, Intelligent system, Mechanical stress, Monolithic integrated circuit, Performance evaluation, Solar cell, Surface topography, Thermal stress.

Abstract

We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass reference. The main integration issues, i.e., adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress, can be resolved while maintaining standard photovoltaic processing. A tight process window is found for the manufacturing of CIGS solar cells on the CMOS side of the microchip. More process margin exists for backside integration.

Links toward previous steps (curation, corpus...)

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to stream Main, to step Repository: 002B42
to stream Chine, to step Extraction: 000803

Links to Exploration step

Pascal:11-0367449

Le document en format XML

<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells</title>
<author><name>JIWU LU</name>
<affiliation wicri:level="4"><inist:fA14 i1="01"><s1>University of Twente</s1>
<s2>7500 AE Enschede</s2>
<s3>NLD</s3>
<sZ>1 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Pays-Bas</country>
<placeName><settlement type="city">Enschede</settlement>
<region nuts="2">Overijssel</region>
</placeName>
<orgName type="university">Université de Twente</orgName>
</affiliation>
</author>
<author><name>WEI LIU</name>
<affiliation wicri:level="1"><inist:fA14 i1="02"><s1>Institute of Photo-electronic Thin Film Device and Technology, Nankai University</s1>
<s2>Tianjin 300071</s2>
<s3>CHN</s3>
<sZ>2 aut.</sZ>
<sZ>4 aut.</sZ>
</inist:fA14>
<country>République populaire de Chine</country>
<wicri:noRegion>Tianjin 300071</wicri:noRegion>
</affiliation>
</author>
<author><name sortKey="Kovalgin, Alexey Y" uniqKey="Kovalgin A">Alexey Y. Kovalgin</name>
<affiliation wicri:level="4"><inist:fA14 i1="01"><s1>University of Twente</s1>
<s2>7500 AE Enschede</s2>
<s3>NLD</s3>
<sZ>1 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Pays-Bas</country>
<placeName><settlement type="city">Enschede</settlement>
<region nuts="2">Overijssel</region>
</placeName>
<orgName type="university">Université de Twente</orgName>
</affiliation>
</author>
<author><name>YUN SUN</name>
<affiliation wicri:level="1"><inist:fA14 i1="02"><s1>Institute of Photo-electronic Thin Film Device and Technology, Nankai University</s1>
<s2>Tianjin 300071</s2>
<s3>CHN</s3>
<sZ>2 aut.</sZ>
<sZ>4 aut.</sZ>
</inist:fA14>
<country>République populaire de Chine</country>
<wicri:noRegion>Tianjin 300071</wicri:noRegion>
</affiliation>
</author>
<author><name sortKey="Schmitz, Jurriaan" uniqKey="Schmitz J">Jurriaan Schmitz</name>
<affiliation wicri:level="4"><inist:fA14 i1="01"><s1>University of Twente</s1>
<s2>7500 AE Enschede</s2>
<s3>NLD</s3>
<sZ>1 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</inist:fA14>
<country>Pays-Bas</country>
<placeName><settlement type="city">Enschede</settlement>
<region nuts="2">Overijssel</region>
</placeName>
<orgName type="university">Université de Twente</orgName>
</affiliation>
</author>
</titleStmt>
<publicationStmt><idno type="inist">11-0367449</idno>
<date when="2011">2011</date>
<idno type="stanalyst">PASCAL 11-0367449 INIST</idno>
<idno type="RBID">Pascal:11-0367449</idno>
<idno type="wicri:Area/Main/Corpus">002B78</idno>
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<idno type="wicri:Area/Chine/Extraction">000803</idno>
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<seriesStmt><idno type="ISSN">0018-9383</idno>
<title level="j" type="abbreviated">IEEE trans. electron devices</title>
<title level="j" type="main">I.E.E.E. transactions on electron devices</title>
</seriesStmt>
</fileDesc>
<profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Adhesion</term>
<term>Back surface</term>
<term>Complementary MOS technology</term>
<term>Copper</term>
<term>Copper selenides</term>
<term>Energy recovery</term>
<term>Gallium selenides</term>
<term>Glass</term>
<term>Indium selenides</term>
<term>Intelligent system</term>
<term>Mechanical stress</term>
<term>Monolithic integrated circuit</term>
<term>Performance evaluation</term>
<term>Solar cell</term>
<term>Surface topography</term>
<term>Thermal stress</term>
</keywords>
<keywords scheme="Pascal" xml:lang="fr"><term>Cellule solaire</term>
<term>Technologie MOS complémentaire</term>
<term>Circuit intégré monolithique</term>
<term>Evaluation performance</term>
<term>Adhérence</term>
<term>Topographie surface</term>
<term>Contrainte thermique</term>
<term>Contrainte mécanique</term>
<term>Surface arrière</term>
<term>Récupération énergie</term>
<term>Système intelligent</term>
<term>Cuivre</term>
<term>Séléniure d'indium</term>
<term>Séléniure de gallium</term>
<term>Verre</term>
<term>Séléniure de cuivre</term>
<term>GaSe</term>
</keywords>
<keywords scheme="Wicri" type="concept" xml:lang="fr"><term>Cuivre</term>
<term>Verre</term>
</keywords>
</textClass>
</profileDesc>
</teiHeader>
<front><div type="abstract" xml:lang="en">We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass reference. The main integration issues, i.e., adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress, can be resolved while maintaining standard photovoltaic processing. A tight process window is found for the manufacturing of CIGS solar cells on the CMOS side of the microchip. More process margin exists for backside integration.</div>
</front>
</TEI>
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<fA03 i2="1"><s0>IEEE trans. electron devices</s0>
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<fA06><s2>8</s2>
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<fA08 i1="01" i2="1" l="ENG"><s1>Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells</s1>
</fA08>
<fA11 i1="01" i2="1"><s1>JIWU LU</s1>
</fA11>
<fA11 i1="02" i2="1"><s1>WEI LIU</s1>
</fA11>
<fA11 i1="03" i2="1"><s1>KOVALGIN (Alexey Y.)</s1>
</fA11>
<fA11 i1="04" i2="1"><s1>YUN SUN</s1>
</fA11>
<fA11 i1="05" i2="1"><s1>SCHMITZ (Jurriaan)</s1>
</fA11>
<fA14 i1="01"><s1>University of Twente</s1>
<s2>7500 AE Enschede</s2>
<s3>NLD</s3>
<sZ>1 aut.</sZ>
<sZ>3 aut.</sZ>
<sZ>5 aut.</sZ>
</fA14>
<fA14 i1="02"><s1>Institute of Photo-electronic Thin Film Device and Technology, Nankai University</s1>
<s2>Tianjin 300071</s2>
<s3>CHN</s3>
<sZ>2 aut.</sZ>
<sZ>4 aut.</sZ>
</fA14>
<fA20><s1>2620-2627</s1>
</fA20>
<fA21><s1>2011</s1>
</fA21>
<fA23 i1="01"><s0>ENG</s0>
</fA23>
<fA43 i1="01"><s1>INIST</s1>
<s2>222F3</s2>
<s5>354000508589360520</s5>
</fA43>
<fA44><s0>0000</s0>
<s1>© 2011 INIST-CNRS. All rights reserved.</s1>
</fA44>
<fA45><s0>38 ref.</s0>
</fA45>
<fA47 i1="01" i2="1"><s0>11-0367449</s0>
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<fA60><s1>P</s1>
</fA60>
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</fA64>
<fA66 i1="01"><s0>USA</s0>
</fA66>
<fC01 i1="01" l="ENG"><s0>We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass reference. The main integration issues, i.e., adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress, can be resolved while maintaining standard photovoltaic processing. A tight process window is found for the manufacturing of CIGS solar cells on the CMOS side of the microchip. More process margin exists for backside integration.</s0>
</fC01>
<fC02 i1="01" i2="X"><s0>001D03F15</s0>
</fC02>
<fC02 i1="02" i2="X"><s0>001D06C02D1</s0>
</fC02>
<fC02 i1="03" i2="X"><s0>001D03F06A</s0>
</fC02>
<fC02 i1="04" i2="X"><s0>230</s0>
</fC02>
<fC03 i1="01" i2="X" l="FRE"><s0>Cellule solaire</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="ENG"><s0>Solar cell</s0>
<s5>01</s5>
</fC03>
<fC03 i1="01" i2="X" l="SPA"><s0>Célula solar</s0>
<s5>01</s5>
</fC03>
<fC03 i1="02" i2="X" l="FRE"><s0>Technologie MOS complémentaire</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="ENG"><s0>Complementary MOS technology</s0>
<s5>02</s5>
</fC03>
<fC03 i1="02" i2="X" l="SPA"><s0>Tecnología MOS complementario</s0>
<s5>02</s5>
</fC03>
<fC03 i1="03" i2="X" l="FRE"><s0>Circuit intégré monolithique</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="ENG"><s0>Monolithic integrated circuit</s0>
<s5>03</s5>
</fC03>
<fC03 i1="03" i2="X" l="SPA"><s0>Circuito integrado monolítico</s0>
<s5>03</s5>
</fC03>
<fC03 i1="04" i2="X" l="FRE"><s0>Evaluation performance</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="ENG"><s0>Performance evaluation</s0>
<s5>04</s5>
</fC03>
<fC03 i1="04" i2="X" l="SPA"><s0>Evaluación prestación</s0>
<s5>04</s5>
</fC03>
<fC03 i1="05" i2="X" l="FRE"><s0>Adhérence</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="ENG"><s0>Adhesion</s0>
<s5>05</s5>
</fC03>
<fC03 i1="05" i2="X" l="SPA"><s0>Adherencia</s0>
<s5>05</s5>
</fC03>
<fC03 i1="06" i2="3" l="FRE"><s0>Topographie surface</s0>
<s5>06</s5>
</fC03>
<fC03 i1="06" i2="3" l="ENG"><s0>Surface topography</s0>
<s5>06</s5>
</fC03>
<fC03 i1="07" i2="X" l="FRE"><s0>Contrainte thermique</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="ENG"><s0>Thermal stress</s0>
<s5>07</s5>
</fC03>
<fC03 i1="07" i2="X" l="SPA"><s0>Tensión térmica</s0>
<s5>07</s5>
</fC03>
<fC03 i1="08" i2="X" l="FRE"><s0>Contrainte mécanique</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="ENG"><s0>Mechanical stress</s0>
<s5>08</s5>
</fC03>
<fC03 i1="08" i2="X" l="SPA"><s0>Tensión mecánica</s0>
<s5>08</s5>
</fC03>
<fC03 i1="09" i2="X" l="FRE"><s0>Surface arrière</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="ENG"><s0>Back surface</s0>
<s5>09</s5>
</fC03>
<fC03 i1="09" i2="X" l="SPA"><s0>Superficie atrás</s0>
<s5>09</s5>
</fC03>
<fC03 i1="10" i2="X" l="FRE"><s0>Récupération énergie</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="ENG"><s0>Energy recovery</s0>
<s5>10</s5>
</fC03>
<fC03 i1="10" i2="X" l="SPA"><s0>Recuperación energía</s0>
<s5>10</s5>
</fC03>
<fC03 i1="11" i2="X" l="FRE"><s0>Système intelligent</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="ENG"><s0>Intelligent system</s0>
<s5>11</s5>
</fC03>
<fC03 i1="11" i2="X" l="SPA"><s0>Sistema inteligente</s0>
<s5>11</s5>
</fC03>
<fC03 i1="12" i2="X" l="FRE"><s0>Cuivre</s0>
<s2>NC</s2>
<s5>22</s5>
</fC03>
<fC03 i1="12" i2="X" l="ENG"><s0>Copper</s0>
<s2>NC</s2>
<s5>22</s5>
</fC03>
<fC03 i1="12" i2="X" l="SPA"><s0>Cobre</s0>
<s2>NC</s2>
<s5>22</s5>
</fC03>
<fC03 i1="13" i2="3" l="FRE"><s0>Séléniure d'indium</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="13" i2="3" l="ENG"><s0>Indium selenides</s0>
<s2>NK</s2>
<s5>23</s5>
</fC03>
<fC03 i1="14" i2="3" l="FRE"><s0>Séléniure de gallium</s0>
<s2>NK</s2>
<s5>24</s5>
</fC03>
<fC03 i1="14" i2="3" l="ENG"><s0>Gallium selenides</s0>
<s2>NK</s2>
<s5>24</s5>
</fC03>
<fC03 i1="15" i2="X" l="FRE"><s0>Verre</s0>
<s5>25</s5>
</fC03>
<fC03 i1="15" i2="X" l="ENG"><s0>Glass</s0>
<s5>25</s5>
</fC03>
<fC03 i1="15" i2="X" l="SPA"><s0>Vidrio</s0>
<s5>25</s5>
</fC03>
<fC03 i1="16" i2="3" l="FRE"><s0>Séléniure de cuivre</s0>
<s2>NK</s2>
<s5>26</s5>
</fC03>
<fC03 i1="16" i2="3" l="ENG"><s0>Copper selenides</s0>
<s2>NK</s2>
<s5>26</s5>
</fC03>
<fC03 i1="17" i2="X" l="FRE"><s0>GaSe</s0>
<s4>INC</s4>
<s5>82</s5>
</fC03>
<fC07 i1="01" i2="X" l="FRE"><s0>Dispositif optoélectronique</s0>
<s5>12</s5>
</fC07>
<fC07 i1="01" i2="X" l="ENG"><s0>Optoelectronic device</s0>
<s5>12</s5>
</fC07>
<fC07 i1="01" i2="X" l="SPA"><s0>Dispositivo optoelectrónico</s0>
<s5>12</s5>
</fC07>
<fN21><s1>249</s1>
</fN21>
<fN44 i1="01"><s1>OTO</s1>
</fN44>
<fN82><s1>OTO</s1>
</fN82>
</pA>
</standard>
</inist>
</record>

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   |texte=   Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells
}}

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Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells

Integration of Solar Cells on Top of CMOS Chips-Part II: CIGS Solar Cells

Descripteurs français

English descriptors

Abstract

Links toward previous steps (curation, corpus...)

Links to Exploration step

Le document en format XML

Pour manipuler ce document sous Unix (Dilib)

Pour mettre un lien sur cette page dans le réseau Wicri